1. Field of the Invention
This invention relates to a bus system for data transmission and, more particularly, to a digital data bus for communication within a digital data processing system.
2. Description of Prior Art
Digital data buses are used in data processing systems, for example, for communication of digital data between a data processor and one or more peripheral devices, such as disc drive memories, terminals, or other data processing units. In general, data buses used in such systems are either synchronous, wherein data transfer is performed in synchronization with a clock signal, or are asychronous, wherein handshake signals synchronize the sending and receiving units.
In a synchronous data bus system, all data transfers are performed in synchronization with a clock signal. That is, the operation of the sending and receiving units is synchronized to the clock. Such systems may utilize either a single frequency clock, or a multiple or variable frequency clock. A single frequency clock system allows the use of simple clock circuitry but data transmission rate, and thus operation of the overall system, is limited to the data rate of the slowest device in the data processing system. In a multiple or variable clock rate system, clock rate is selected to be that of the slower of the sending or receiving units currently communicating. Data rate may, however, be selected to be the highest achievable with the particular units which are communicating. A multiple or variable data rate synchronous system is, in general, more complex than a single clock rate system since the clock circuitry must be capable of generating a multiplicity of clock frequencies. Also, before data communication can be performed the sending and receiving units must communicate to select a clock rate.
In an asychronous data bus system, as stated above, transfer of data between a sending and a receiving unit is synchronized by handshake signals. That is, a sending unit places data on the bus and transmits a handshake signal to the receiving unit indicating that data is present on the bus. When the receiving unit is ready to accept the data, the receiving unit accepts the data and transmits a handshake signal to the sending unit indicating that the data has been accepted. An asynchronous data bus system thereby allows greater flexibility of data rate and the data rate may be the maximum achievable between a particular sending and receiving unit pair. An asynchronous data bus system is in general, however, more complex than a synchronous system due to the requirement to exchange handshake signals between sending and receiving units. In addition, maximum data rate may not be achievable due to the requirement to resynchronize the data transferred at the sending and receiving units. That is, data must first be transferred from, for example, a disc drive, to a sending unit, then from sending unit to receiving unit, and finally from receiving unit to, for example, a data processor. Additional delays in data transmission will thereby be imposed at the sending end of the bus in transferring data from the peripheral device to the sending unit, and from the sending unit to the bus. This delay occurs because data transfer between the peripheral device and the sending unit is not synchronized with transfer of data from the sending unit to the data bus. Similarly, additional data transmission delays may be imposed at the receiving end because reception of data by the receiving unit is not synchronized with transfer of data between the receiving unit and the data processor.
The present invention provides a solution to these problems of the prior art as will be discussed in detail hereinbelow.